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authorWillaWillNot <[email protected]>2025-11-21 16:38:34 -0500
committerWillaWillNot <[email protected]>2025-11-21 16:39:10 -0500
commita5f7764eb4f01a0668cbd3b534cde486b97f5ba4 (patch)
tree1dde242388f703630d4a2ecc34c95df459ccf2c1 /examples
parent623623a25f213f76de932eaf4458c3120823d205 (diff)
parent96a026c73bad2ebb8dfc78e88c9690611bf2cb97 (diff)
Synchronize with main branch
Diffstat (limited to 'examples')
-rw-r--r--examples/stm32u5/src/bin/adc.rs2
-rw-r--r--examples/stm32wba6/src/bin/adc.rs28
2 files changed, 28 insertions, 2 deletions
diff --git a/examples/stm32u5/src/bin/adc.rs b/examples/stm32u5/src/bin/adc.rs
index ad59c0bea..4d2d93aa2 100644
--- a/examples/stm32u5/src/bin/adc.rs
+++ b/examples/stm32u5/src/bin/adc.rs
@@ -31,7 +31,7 @@ async fn main(_spawner: embassy_executor::Spawner) {
31 31
32 // **** ADC4 init **** 32 // **** ADC4 init ****
33 let mut adc4 = Adc::new_adc4(p.ADC4); 33 let mut adc4 = Adc::new_adc4(p.ADC4);
34 let mut adc4_pin1 = p.PC1; // A4 34 let mut adc4_pin1 = p.PC1.degrade_adc(); // A4
35 let mut adc4_pin2 = p.PC0; // A5 35 let mut adc4_pin2 = p.PC0; // A5
36 adc4.set_resolution_adc4(adc4::Resolution::BITS12); 36 adc4.set_resolution_adc4(adc4::Resolution::BITS12);
37 adc4.set_averaging_adc4(adc4::Averaging::Samples256); 37 adc4.set_averaging_adc4(adc4::Averaging::Samples256);
diff --git a/examples/stm32wba6/src/bin/adc.rs b/examples/stm32wba6/src/bin/adc.rs
index 9d1f39419..51dcff57a 100644
--- a/examples/stm32wba6/src/bin/adc.rs
+++ b/examples/stm32wba6/src/bin/adc.rs
@@ -2,12 +2,38 @@
2#![no_main] 2#![no_main]
3 3
4use defmt::*; 4use defmt::*;
5use embassy_stm32::Config;
5use embassy_stm32::adc::{Adc, AdcChannel, SampleTime, adc4}; 6use embassy_stm32::adc::{Adc, AdcChannel, SampleTime, adc4};
7use embassy_stm32::rcc::{
8 AHB5Prescaler, AHBPrescaler, APBPrescaler, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk, VoltageScale,
9};
6use {defmt_rtt as _, panic_probe as _}; 10use {defmt_rtt as _, panic_probe as _};
7 11
8#[embassy_executor::main] 12#[embassy_executor::main]
9async fn main(_spawner: embassy_executor::Spawner) { 13async fn main(_spawner: embassy_executor::Spawner) {
10 let config = embassy_stm32::Config::default(); 14 let mut config = Config::default();
15 // Fine-tune PLL1 dividers/multipliers
16 config.rcc.pll1 = Some(embassy_stm32::rcc::Pll {
17 source: PllSource::HSI,
18 prediv: PllPreDiv::DIV1, // PLLM = 1 → HSI / 1 = 16 MHz
19 mul: PllMul::MUL30, // PLLN = 30 → 16 MHz * 30 = 480 MHz VCO
20 divr: Some(PllDiv::DIV5), // PLLR = 5 → 96 MHz (Sysclk)
21 // divq: Some(PllDiv::DIV10), // PLLQ = 10 → 48 MHz (NOT USED)
22 divq: None,
23 divp: Some(PllDiv::DIV30), // PLLP = 30 → 16 MHz (USBOTG)
24 frac: Some(0), // Fractional part (enabled)
25 });
26
27 config.rcc.ahb_pre = AHBPrescaler::DIV1;
28 config.rcc.apb1_pre = APBPrescaler::DIV1;
29 config.rcc.apb2_pre = APBPrescaler::DIV1;
30 config.rcc.apb7_pre = APBPrescaler::DIV1;
31 config.rcc.ahb5_pre = AHB5Prescaler::DIV4;
32
33 // voltage scale for max performance
34 config.rcc.voltage_scale = VoltageScale::RANGE1;
35 // route PLL1_P into the USB‐OTG‐HS block
36 config.rcc.sys = Sysclk::PLL1_R;
11 37
12 let mut p = embassy_stm32::init(config); 38 let mut p = embassy_stm32::init(config);
13 39