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path: root/embassy-stm32/src/timer/low_level.rs
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* docxoviat2025-12-031-0/+3
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* timer: restore waveform methodxoviat2025-12-031-4/+21
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* timer: clamp compare value before dmaxoviat2025-12-011-0/+12
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* timer: allow 16 bit dma buffers for 32 bit timers.xoviat2025-12-011-10/+10
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* stm32: use typelevel timer typexoviat2025-11-271-120/+71
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* timer: add writable ring bufferxoviat2025-11-251-1/+34
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* cleanup low-level timer methodsxoviat2025-11-251-92/+45
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* stm32: remove waveform methodxoviat2025-11-251-37/+0
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* timer: add note about disruptionxoviat2025-11-151-1/+2
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* Merge branch 'timer_update_management' of github.com:WattStep/embassy into timexoviat2025-11-151-8/+10
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| * Add separate method for generating update event. Make sure values are loaded ↵Jakob2025-11-151-8/+18
| | | | | | | | into shadow registers before starting the timer.
| * Avoid generating update events when chaning timer period. Set frequency ↵Jakob2025-11-151-16/+8
| | | | | | | | update methods to return applied ARR values which then can be used for calcualting new CCR values.
* | Move dma waveform methods down to low level timerAlbin Hedman2025-11-151-1/+214
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* Implement into_ring_buffered for g4. Add methods for configuring injected ↵Jakob2025-11-041-0/+10
| | | | sampling for g4.
* timer/low_level: add ability to set master modexoviat2025-10-281-1/+6
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* timer: add output compare valuesxoviat2025-10-271-10/+59
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* Add get methods for meo, ossi and ossrJakob2025-08-101-0/+15
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* Add methods for setting ossi, ossr, osi and oisn along with software trigger ↵Jakob2025-08-101-0/+25
| | | | for break input
* Merge pull request #4044 from yodaldevoid/stm32-opm-timerDario Nieuwenhuis2025-04-061-0/+30
|\ | | | | STM32: One pulse mode timer
| * stm32/timer: Support one pulse modeGabriel Smith2025-04-041-0/+30
| | | | | | | | | | Currently does not support output pins so it really is only useful to create delayed interrupts based on external signals.
* | Remove Peripheral trait, rename PeripheralRef->Peri.Dario Nieuwenhuis2025-03-271-5/+3
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* Merge pull request #3704 from CNLHC/pwm_support_gp32Dario Nieuwenhuis2025-01-211-0/+5
|\ | | | | | | feat: Add 32-bit timer support for waveform function
| * dev: change name to bitsLiu Hancheng2025-01-021-1/+1
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| * doc: add doc for timer get_bits fnLiu Hancheng2025-01-011-0/+1
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| * feat: Add 32-bit timer support for waveform functionLiu Hancheng2025-01-011-0/+4
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* | chore: fix buildelagil2025-01-031-20/+20
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* stm32/timer: avoid max_compare_value >= u16::MAXAurélien Jacobs2024-11-201-8/+16
| | | | | | | | | | With STM32 32 bits timers, the max_compare_value (AKA, ARR register) can currently be set greater than u16::MAX, which leads to the following assert!(max < u16::MAX as u32) in max_duty_cycle() when setting up a 1 kHz SimplePwm on 84 MHz MCU. The issue is fixed by forcing a max_compare_value that fits into 16 bits when setting the frequency for a PWM.
* Make clone_unchecked workGrant Miller2024-09-211-3/+1
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* wip: split by valueGrant Miller2024-09-071-0/+9
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* Merge pull request #3014 from brunob45/pwm_inputDario Nieuwenhuis2024-05-311-0/+28
|\ | | | | | | Add PWM Input for STM32
| * rust fmt really does not want blank space thereBruno Bousquet2024-05-301-1/+0
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| * fix fmt (again)Bruno Bousquet2024-05-301-2/+3
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| * fix fmtBruno Bousquet2024-05-301-3/+1
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| * create functions in inner to handle register modificationBruno Bousquet2024-05-301-0/+14
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| * pwm_input is working on F446Bruno Bousquet2024-05-291-0/+16
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* | stm32/rcc: replace generated enable/disable code with runtime infoJan Špaček2024-05-251-2/+3
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* add get_input_interruptBruno Bousquet2024-05-051-0/+5
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* stm32/timer: add `low_level::Timer::get_clock_frequency()`Jan Špaček2024-05-041-0/+5
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* stm32 timer: fix 32bit timer off by 1 ARR errorftk2024-04-271-1/+4
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* stm32/timer: simplify traits, convert from trait methods to struct.Dario Nieuwenhuis2024-03-231-0/+638
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