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* low-power: use scoped block stopxoviat2025-12-081-4/+4
| | | | Co-authored-by: hjeldin <[email protected]>
* stm32: extract busychannel into common apixoviat2025-11-251-8/+4
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* stm32: allow granular stop for uartxoviat2025-11-252-4/+19
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* fix: fix incorrect logic for buffered usart transmission complete.xoviat2025-11-181-1/+1
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* remove csxoviat2025-10-301-13/+10
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* stm32/uart: fix rb uart racexoviat2025-10-291-9/+4
| | | | closes #4682
* Rustfmt for edition 2024.Dario Nieuwenhuis2025-10-063-11/+11
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* STM32: USART: Change eager_reads from bool to Option<usize>Adam Greig2025-10-013-31/+64
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* STM32: USART: Make BufferedUartRx return all available bytes when they wrap ↵Adam Greig2025-10-011-14/+23
| | | | around the internal buffer end
* STM32: USART: Add de_assertion_time and de_deassertion_time configsAdam Greig2025-10-011-0/+42
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* STM32: USART: Add `eager_reads` config optionAdam Greig2025-10-013-47/+95
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* stm32/usart: fix blocking flushBirk Tjelmeland2025-09-101-1/+3
| | | | | | | The PR in #2416 fixes buffered usart flushing, but only for the async functions. This commit introduces the same fixes to the blocking functions.
* stm32/afio: make the A generic param only appear in chips with AFIO.Dario Nieuwenhuis2025-09-052-76/+76
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* Add STM32F1 AFIO remapFabian Wolter2025-09-052-82/+82
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* fix: buildelagil2025-09-051-2/+2
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* feat: add new_with_table() initializer for ring-buffers and removal of ↵etiennecollin2025-09-051-3/+2
| | | | | | | | | | | | | | | | RegisterUpdaters - It is now possible to pass a linked-list table to the ring-buffer with the `new_with_table()` function or use the `new()` function for a basic ring-buffer setup. - A `simple_ring_buffer_table()` function was added to the read and write ring-buffers to generate the same table as the one created by `new()` in case the user only wants to customize the default table options. - RegisterUpdaters have been removed as the user now has direct access to the table and its items if needed. See: https://github.com/elagil/embassy/pull/1#issuecomment-2891997294
* feat: custom dma configuration using RegisterUpdaters structetiennecollin2025-09-051-1/+2
| | | | | See this PR comment: https://github.com/embassy-rs/embassy/pull/3923#issuecomment-2889283939
* fix: modified dma channel state managementetiennecollin2025-09-051-1/+1
| | | | | See https://github.com/embassy-rs/embassy/pull/3923#discussion_r2094570176
* feat: wip, write buffer in halveselagil2025-09-051-1/+1
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* feat: gpdma support (wip)elagil2025-09-051-2/+0
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* Fix stm32 buffered half-duplex uart receivechemicstry2025-07-162-1/+3
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* Fix impl embedded_hal_nb::serial::Write for embassy_stm32::usart::UartTxqwerty191062025-07-031-1/+15
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* Merge pull request #4251 from kpfleming/improve-stm32-ringbuffereduart-docsDario Nieuwenhuis2025-06-011-8/+71
|\ | | | | | | stm32: Expand documentation of RingBufferedUartRx.
| * Move new documentation to RingBufferedUartRx struct.Kevin P. Fleming2025-05-241-56/+62
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| * stm32: Expand documentation of RingBufferedUartRx.Kevin P. Fleming2025-05-241-8/+65
| | | | | | | | | | | | | | | | Explain to users of this driver how 'waiting for bytes' actually works, and what that may mean for latency introduced in their application. Also correct references to 'start' to be 'start_uart'.
* | stm32: Assert in BufferedUart that the buffers are not empty.Kevin P. Fleming2025-05-251-0/+2
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* Merge pull request #3965 from toon23/stm32_usart-pin_configDario Nieuwenhuis2025-04-182-91/+83
|\ | | | | | | Stm32 usart: implement pin config for cts, tx, rts and de
| * Stm32 usart: better names for open drain pin modesAnton Pöhl2025-04-161-6/+6
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| * Stm32 usart: Remove meaningless pin configurationsAnton Pöhl2025-04-121-10/+0
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| * FormatAnton Pöhl2025-04-112-23/+5
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| * Stm32 usart: remove HalfDuplexConfigAnton Pöhl2025-04-112-38/+8
| | | | | | | | The pin parameters of usart::Config are used instead.
| * Stm32 usart: make pin modes of cts, tx, rts and de configurableAnton Pöhl2025-04-112-34/+84
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* | fix(stm32): handle half-duplex in ringbuffered readBadr Bouslikhin2025-04-062-1/+10
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* | BufferedUart initializationMichael Gomez2025-04-041-5/+5
| | | | | | | | | | | | | | This change modifies UART initialization throughout Embassy to take pins before interrupts. Related to #1304.
* | Merge branch 'main' into fix/ringbuffered-error-handling to resolve merge ↵Tobias Naumann2025-03-313-130/+130
|\ \ | | | | | | | | | conflicts
| * \ Merge pull request #3968 from ↵Ulf Lilleengen2025-03-311-11/+38
| |\ \ | | |/ | |/| | | | | | | | | | embedded-rust-iml/feature/ringbuffered-embedded-hal-nb Add embedded_hal_nb::serial::Read impl for RingBufferedUartRx
| * | Remove Peripheral trait, rename PeripheralRef->Peri.Dario Nieuwenhuis2025-03-273-130/+130
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* | | Cleanup stm32_metapac register usage in usart moduleTobias Naumann2025-03-271-3/+3
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* | | Fix unused importsTobias Naumann2025-03-272-11/+2
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* | | Check and clear idle and error flags togetherTobias Naumann2025-03-211-40/+39
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* | | Use write closure to clear idle flag, only read rdr on usart versions which ↵Tobias Naumann2025-03-211-7/+6
| |/ |/| | | | | need it
* | Add embedded_hal_nb::serial::Read impl for RingBufferedUartRxTobias Naumann2025-03-211-11/+38
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* Recover from errors in ringbuffered usartTobias Naumann2025-03-201-5/+10
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* fixRogan Morrow2025-02-281-3/+1
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* fixRogan Morrow2025-02-281-2/+3
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* add missing moduleRogan Morrow2025-02-281-0/+1
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* feature flagRogan Morrow2025-02-281-3/+6
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* add separate tx wakerRogan Morrow2025-02-281-1/+4
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* only clear idle flagRogan Morrow2025-02-281-1/+3
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* Implement `core::error::Error` for STM32 Serial DevicesGuy Marino2025-02-261-0/+16
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