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* stm32/spi: check that the RCC enable bit is disabled on drop.Dario Nieuwenhuis2024-05-201-0/+8
* stm32/tests: add stm32u0 hil.Dario Nieuwenhuis2024-05-133-1/+31
* tests/riscv32: workaround linking bug, update deps.Dario Nieuwenhuis2024-05-132-2/+216
* stm32: add support for STM32H7[RS] "bootflash line", add HIL tests.Dario Nieuwenhuis2024-05-017-5/+62
* stm32: update metapac. Adds U5 LPDMA, fixes ADC_COMMONs.Dario Nieuwenhuis2024-04-292-4/+4
* low power for h5eZio Pan2024-04-282-2/+9
* Reduce use of the full `futures` crate.Dario Nieuwenhuis2024-04-261-1/+0
* Remove leftover `cargo new` boilerplate.Dario Nieuwenhuis2024-04-262-4/+0
* stm32: can: fd: fix test build for all relevant chipsTorin Cooper-Bennun2024-04-222-6/+18
* stm32/usart: remove DMA generic params.Dario Nieuwenhuis2024-04-162-6/+5
* stm32/spi: remove DMA generic params.Dario Nieuwenhuis2024-04-151-3/+2
* stm32: update adc examplesAndres Vahter2024-04-101-2/+2
* Add parameter for enabling pull-up and pull-down in RP PWM input modepawel001002024-04-051-3/+43
* Merge pull request #2697 from eZioPan/stm32-cordicDario Nieuwenhuis2024-04-043-5/+147
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| * stm32 CORDIC: exclude stm32u5aeZio Pan2024-03-261-1/+1
| * stm32 CORDIC: add g491re back to cordic testeZio Pan2024-03-232-9/+4
| * stm32 CORDIC: re-design APIeZio Pan2024-03-231-62/+48
| * stm32 CORDIC: make HIL runeZio Pan2024-03-231-12/+14
| * stm32 CORDIC: add HIL testeZio Pan2024-03-233-4/+163
* | rename PWM_CH to PWM_SLICEAlexandru RADOVICI2024-04-021-7/+7
* | stm32/can: simplify bxcan api, merging bx::* into the main structs.Dario Nieuwenhuis2024-04-021-10/+9
* | CAN: Use the same testing code for BXCAN and FDCAN h/w.Corey Schuhen2024-03-283-194/+163
* | CAN: Unify API's between BXCAN and FDCAN. Use Envelope for all read methods i...Corey Schuhen2024-03-281-12/+12
* | Remove ad-hoc fixes for setting the IOSV bit to trueEmilie Burgun2024-03-261-7/+0
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* Fix warnings in recent nightly.Dario Nieuwenhuis2024-03-203-12/+24
* FDCAN: Fix offset issue preventing CAN2 and CAN3 from working.Corey Schuhen2024-03-161-2/+51
* Merge pull request #2701 from timokroeger/stm32-ucpdDario Nieuwenhuis2024-03-152-1/+127
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| * tests/stm32: run ucpd only on g0.Dario Nieuwenhuis2024-03-152-1/+2
| * [UCPD] Add unit test for stm32g071rb boardTimo Kröger2024-03-152-1/+126
* | Use Result instead of Option for Frame creation.Corey Schuhen2024-03-131-1/+1
* | Shared frame types.Corey Schuhen2024-03-131-2/+2
* | Merge pull request #2691 from caleb-garrett/cryp-dmaDario Nieuwenhuis2024-03-122-10/+21
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| * | rustfmtCaleb Garrett2024-03-121-5/+2
| * | Correct cryp CI build issues.Caleb Garrett2024-03-121-2/+4
| * | Add async CRYP to test.Caleb Garrett2024-03-122-10/+22
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* / Make use of internal BXCAN crate work. Tested on stm32f103 with real bus and ...Corey Schuhen2024-03-071-2/+2
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* stm32/rcc: port c0 to new api. Add c0 HSIKER/HSISYS support.Dario Nieuwenhuis2024-03-041-0/+11
* stm32/rcc: port g0 to new api.Dario Nieuwenhuis2024-03-041-0/+13
* stm32/rcc: g4: consistent PllSource, add pll pqr limits, simplify a bit.Dario Nieuwenhuis2024-03-041-1/+1
* stm32: autogenerate mux config for all chips.Dario Nieuwenhuis2024-03-012-26/+25
* Remove CRYP from F429.Caleb Garrett2024-02-291-1/+1
* Remove CRYP from H7A3.Caleb Garrett2024-02-291-1/+1
* Fix H7 CRYP operation.Caleb Garrett2024-02-291-2/+2
* Run gen_test.pyCaleb Garrett2024-02-251-1/+1
* rustfmtCaleb Garrett2024-02-251-3/+1
* Add CRYP test.Caleb Garrett2024-02-252-2/+80
* stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.Dario Nieuwenhuis2024-02-261-7/+7
* FDCAN: Don't require internal module for public API.Corey Schuhen2024-02-251-2/+2
* stm32/dma: add AnyChannel, add support for BDMA on H7.Dario Nieuwenhuis2024-02-241-1/+1
* stm32/tests: run stm32u5a5zj from flash due to wrong RAM size in stm32-data.Dario Nieuwenhuis2024-02-232-1/+2
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