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* | | fix buildgoueslati2023-06-121-5/+6
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* | | Remove embassy-cortex-m crate, move stuff to embassy-hal-common.Dario Nieuwenhuis2023-06-092-2/+2
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* | | tests/rp: make cyw43-perf less strict.Dario Nieuwenhuis2023-06-081-3/+3
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* | | tests/rp: update cyw43-perf for embassy-net changes.Dario Nieuwenhuis2023-06-081-2/+2
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* | | cyw43: add perf HIL test.Dario Nieuwenhuis2023-06-066-1/+397
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* | | tests/rp: enable run-from-ram.Dario Nieuwenhuis2023-06-061-1/+1
| |/ |/| | | | | Otherwise the flash test is flaky because it attempts to use boot2.
* | ci: run HIL tests in parallel.Dario Nieuwenhuis2023-05-3040-60/+124
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*-. \ Merge #1489 #1500bors[bot]2023-05-295-41/+22
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1489: stm32/ipcc: make IPCC methods static r=xoviat a=OueslatiGhaith 1500: stm32/tests: disable sdmmc test for now r=xoviat a=xoviat Co-authored-by: goueslati <[email protected]> Co-authored-by: Ghaith Oueslati <[email protected]> Co-authored-by: xoviat <[email protected]>
| | * stm32/tests: disable sdmmc test for nowxoviat2023-05-291-1/+1
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| * tests/stm32: revert cfg changesxoviat2023-05-271-5/+3
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| * stm32/ipcc: refactor examples and testsxoviat2023-05-274-13/+19
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| * stm32/ipcc: extract tl_mbox linker file to embassy-stm32xoviat2023-05-271-23/+0
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| * stm32/ipcc: update testgoueslati2023-05-261-9/+9
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* stm32: move to bind_interruptsxoviat2023-05-244-118/+121
| | | | disable lora functionality for now
* Merge #1457bors[bot]2023-05-233-3/+33
|\ | | | | | | | | | | | | | | | | | | | | | | | | 1457: TL Mbox read and write for stm32wb r=xoviat a=OueslatiGhaith Hello, This pull request is related to #1397 and #1401, inspired by #24, built upon the work done in #1405 and #1424, and was tested on an stm32wb55rg. This pull request aims to add read and write functionality to the TL mailbox for stm32wb microcontrollers Co-authored-by: goueslati <[email protected]> Co-authored-by: xoviat <[email protected]>
| * stm32/ipcc: disable testxoviat2023-05-221-1/+1
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| * stm32/ipcc: fix hil testxoviat2023-05-213-5/+29
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| * stm32/ipcc: enable testxoviat2023-05-211-1/+1
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| * updated test casegoueslati2023-05-191-1/+7
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* | Add HIL testkalkyl2023-05-161-0/+9
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* | Merge #1458bors[bot]2023-05-153-20/+32
|\ \ | | | | | | | | | | | | | | | | | | | | | 1458: rp: remove take!, add bind_interrupts! r=Dirbaio a=pennae both of the uart interrupts now check a flag that only the dma rx path ever sets (and now unsets again on drop) to return early if it's not as they expect. this is ... not our preferred solution, but if bind_interrupts *must* allow mutiple handlers to be specified then this is the only way we can think of that doesn't break uarts. Co-authored-by: pennae <[email protected]>
| * | rp: remove take!, add bind_interrupts!pennae2023-05-153-20/+32
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* / stm32 uart: Add a test for blocking RX overflowTimo Kröger2023-05-141-1/+21
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* Merge #1424bors[bot]2023-05-112-0/+57
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | 1424: add TL maibox for stm32wb r=xoviat a=OueslatiGhaith Hello, This pull request is related to #1397 and #1401, inspired by #24, build upon the work done in #1405, and was tested on an stm32wb55rg. This pull request aims to add the transport layer mailbox for stm32wb microcontrollers. For now it's only capable of initializing it and getting the firmware information Co-authored-by: goueslati <[email protected]> Co-authored-by: Ghaith Oueslati <[email protected]> Co-authored-by: xoviat <[email protected]>
| * stm32/ble: fix tests and add instructions to run examplexoviat2023-05-111-1/+1
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| * stm32/tests: add hil test for blexoviat2023-05-032-1/+58
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* | stm32/test: remove adsfaDario Nieuwenhuis2023-05-021-1/+0
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* | stm32/test: F1 no longer fits in RAM.Dario Nieuwenhuis2023-05-021-1/+1
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* | stm32/test: workaround #1426Dario Nieuwenhuis2023-05-022-2/+8
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* | stm32/usart: add baudrate calc test.Dario Nieuwenhuis2023-05-024-24/+72
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* | Merge #1423bors[bot]2023-05-021-0/+63
|\ \ | |/ |/| | | | | | | | | | | 1423: rp: fix gpio InputFuture and inefficiencies r=pennae a=pennae InputFuture could not wait for edges without breaking due to a broken From impl, but even if the impl had been correct it would not have worked correctly because raw edge interrupts are sticky and must be cleared from software. also replace critical sections with atomic accesses, and do nvic setup only once. Co-authored-by: pennae <[email protected]>
| * rp/gpio: set up gpio interrupts only oncepennae2023-05-021-0/+63
| | | | | | | | | | | | doing this setup work repeatedly, on every wait, is unnecessary. with nothing ever disabling the interrupt it is sufficient to enable it once during device init and never touch it again.
* | Merge #1422bors[bot]2023-05-021-4/+0
|\ \ | | | | | | | | | | | | | | | | | | | | | 1422: rp: remove leftovers from #1414 r=Dirbaio a=pennae forgot to remove these when they were no longer necessary or useful. oops. Co-authored-by: pennae <[email protected]>
| * | rp: remove leftovers from #1414pennae2023-05-021-4/+0
| |/ | | | | | | forgot to remove these when they were no longer necessary or useful. oops.
* | stm32/test: fix race condition in uart_dma.Dario Nieuwenhuis2023-05-011-9/+18
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* | stm32/test: cleanup ringbuffer test, exit on success (transferring 100kb)Dario Nieuwenhuis2023-05-011-39/+38
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* | stm32/test: add real defmt timestampDario Nieuwenhuis2023-05-012-12/+2
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* | stm32/uart: feature-gate ringbuffer out when using gpdma, not supported yet.Dario Nieuwenhuis2023-05-012-7/+15
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* | Support overflow detection for more than one ring-periodRasmus Melchior Jacobsen2023-05-012-11/+23
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* | Ring-buffered uart rx with one-period overrun detectionRasmus Melchior Jacobsen2023-05-014-0/+252
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* | Merge #1376bors[bot]2023-05-012-1/+61
|\ \ | |/ |/| | | | | | | | | | | 1376: rtc: cleanup and consolidate r=Dirbaio a=xoviat This removes an extra file that I left in, adds an example, and consolidates the files into one 'v2' file. Co-authored-by: xoviat <[email protected]>
| * stm32/rtc: fix datetime and add f4 testxoviat2023-04-252-1/+61
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* | rp/uart: report errors from dma receivepennae2023-05-011-10/+228
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* | rp/uart: report errors from buffered uartpennae2023-05-011-20/+229
| | | | | | | | | | | | | | | | | | this reports errors at the same location the blocking uart would, which works out to being mostly exact (except in the case of overruns, where one extra character is dropped). this is actually easier than going nuclear in the case of errors and nuking both the buffer contents and the rx fifo, both of which are things we'd have to do in addition to what's added here, and neither are needed for correctness.
* | tests/rp: test error conditions for uartpennae2023-05-011-11/+148
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* | tests/rp: fix buffered uart testpennae2023-05-011-3/+3
| | | | | | | | | | | | the rp uart receive fifo is 32 entries deep, so the 31 byte test data fits into it without needing any buffering. extend to 48 bytes to fill the entire fifo and the 16 byte test buffer.
* | Bump versions preparing for -macros and -executor releaseUlf Lilleengen2023-04-274-4/+4
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* | rp: add PWM apipennae2023-04-231-0/+142
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* | rp: hook up softfloat rom intrinsicspennae2023-04-193-3/+58
|/ | | | | | rp-hal has done this very well already, so we'll just copy their entire impl again. only div.rs needed some massaging because our sio access works a little differently, everything else worked as is.
* stm32/sdmmc: add hil test for f4.Dario Nieuwenhuis2023-04-173-1/+234
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