aboutsummaryrefslogtreecommitdiff
Commit message (Expand)AuthorAgeFilesLines
* Fix compile for stm32wbchemicstry2022-03-182-2/+2
* Fix RCC safety and add reset to DACchemicstry2022-03-183-23/+43
* Reset peripherals on enablechemicstry2022-03-183-0/+3
* Merge #670bors[bot]2022-03-171-5/+8
|\
| * Add commentschemicstry2022-03-171-0/+4
| * Make UART futures Sendchemicstry2022-03-171-5/+4
|/
* Merge #668bors[bot]2022-03-151-1/+1
|\
| * Update chiptool.Dario Nieuwenhuis2022-03-151-1/+1
* | Merge #667bors[bot]2022-03-155-82/+12
|\ \ | |/ |/|
| * Remove duplicate stm32-metapac/src/common.rs with chiptoolNicolas Viennot2022-03-155-82/+12
* | Merge #665bors[bot]2022-03-151-0/+9
|\ \
| * | Rebuild when the chip definition changesNicolas Viennot2022-03-151-0/+9
* | | Merge #661bors[bot]2022-03-152-74/+250
|\ \ \ | |_|/ |/| |
| * | Add support for splitting stm32 usart into TX and RXUlf Lilleengen2022-03-152-74/+250
|/ /
* | Merge #666bors[bot]2022-03-152-1/+24
|\ \ | |/ |/|
| * stm32/spi: fix blocking transfer hanging after async.Dario Nieuwenhuis2022-03-152-0/+20
| * stm32/spi: Clear rx fifo in blocking methodsGrant Miller2022-03-141-1/+4
|/
* Merge #664bors[bot]2022-03-153-35/+84
|\
| * stm32/spi: do not clear rxfifo in SPIv3, the hw already does it.Dario Nieuwenhuis2022-03-151-2/+7
| * stm32/spi: fix hang in SPIv3 by not waiting for rxfifo empty in finish_dma.Dario Nieuwenhuis2022-03-151-25/+8
| * stm32/spi: check zero-length trasnfers.Dario Nieuwenhuis2022-03-152-0/+12
| * stm32/spi: more exhaustive test.Dario Nieuwenhuis2022-03-152-0/+27
| * stm32/spi: implement async trasnfer_in_placeDario Nieuwenhuis2022-03-152-8/+30
|/
* Merge #663bors[bot]2022-03-141-9/+18
|\
| * rustfmtGrant Miller2022-03-141-3/+3
| * Fix zero-length-slice bugsGrant Miller2022-03-141-5/+15
| * Fix async `write` bugGrant Miller2022-03-141-4/+3
|/
* Merge #662bors[bot]2022-03-144-510/+212
|\
| * Make all functions generic over word sizeGrant Miller2022-03-141-21/+27
| * Use const REGSGrant Miller2022-03-141-63/+55
| * Finish unificationGrant Miller2022-03-144-454/+118
| * Finish matching versionsGrant Miller2022-03-143-0/+27
| * Add `set_txdmaen` and `set_rxdmaen` functionsGrant Miller2022-03-144-45/+41
| * Add `flush_rx_fifo` functionGrant Miller2022-03-144-20/+37
| * Call `set_word_size` before disabling SPEGrant Miller2022-03-142-6/+6
|/
* Merge #660bors[bot]2022-03-141-0/+1
|\
| * Tell bors to delete merged branchesGrant Miller2022-03-141-0/+1
|/
* Merge #627bors[bot]2022-03-1033-837/+714
|\
| * Update rust nightly, embedded-hal 1.0, embedded-hal-async.Dario Nieuwenhuis2022-03-1133-837/+714
|/
* Merge #647bors[bot]2022-03-092-0/+12
|\
| * stm32/dma: panic on DMA error.Dario Nieuwenhuis2022-03-092-0/+12
|/
* Merge #640bors[bot]2022-03-095-50/+238
|\
| * Move EasyDMA documentation to module levelTil Blechschmidt2022-03-084-38/+53
| * Fix inverted boolean conditionTil Blechschmidt2022-03-081-1/+1
| * Refactor _from_ram methods to use more readable copy operationTil Blechschmidt2022-03-023-23/+18
| * Change TWIM methods to copy slice if required and add non-copying variantsTil Blechschmidt2022-03-021-41/+86
| * Change UARTE methods to copy slice if required and add non-copying variantsTil Blechschmidt2022-03-021-1/+35
| * Fix EasyDMA slice copying not actually copying dataTil Blechschmidt2022-02-231-4/+7
| * Change slice length check to use stable methodTil Blechschmidt2022-02-232-2/+3
| * Add defmt log outputs for SPIM memcpyTil Blechschmidt2022-02-231-0/+2
generated by cgit (git 2.34.1) at 2026-04-06 05:02:31 +0000